This invention relates to a semiconductor memory device, and, more particularly, to a control for simultaneously writing data into a plurality of memory cells in a random access memory (RAM).
A prior art static random-access memory (abbreviated to SRAM) has the configuration shown in FIG. 1. In the figure, reference numeral 11 denotes an address input terminal for receiving address signal Add. Numeral 12 denotes an address input circuit for receiving address signal Add input from address input terminal 11. Numeral 13 denotes a row decoder for decoding a row address signal supplied from address input circuit 12. Numeral 14 denotes a plurality of word lines. One of the word lines 14 is selected and driven by the output of row decoder 13. Numerals 15.sub.1 and 15.sub.2 denote a plurality of paired bit lines crossing word lines 14. Numeral 16 denotes a plurality of precharge circuits respectively provided between pairs of bit lines 15.sub.1 and 15.sub.2, on one hand, and precharge power source Vpc terminal 17 (which may be of high-potential power source V.sub.DD), on the other hand. Numeral 18 denotes a plurality of static memory cells. Memory cells 18 are respectively connected to paired bit lines 15.sub.1 and 15.sub.2 arrayed in rows and word lines arrayed orthogonally to the bit lines. Numeral 19 denotes sense amplifiers. One sense amplifier is connected to each pair of bit lines 15.sub.1 and 15.sub.2. Numeral 20 denotes writing circuits. One writing circuit is connected to one pair of bit lines 15.sub.1 and 15.sub.2. Numeral 21 denotes a write control circuit for controlling the write operation of writing circuits 20 by write signal WS from write signal terminal 22. Numeral 23 denotes a column decoder for decoding a column address signal supplied from address input circuit 12, to select and drive each pair of bit lines 15.sub.1 and 15.sub.2. Numeral 24 denotes a data input/output circuit for transferring data D, via data input/output terminal 25, from writing circuit 20 and bit lines 15.sub.1 and 15.sub.2 to an external apparatus and vice versa.
Precharge circuit 16, memory cells 18, writing circuit 20 have configurations shown in FIG. 2, for example. Precharge circuit 16 includes P-channel MOS FETs (metal oxide semiconductor field effect transistors) Q1 and Q2. The sources of transistors Q1 and Q2 are connected to precharge power source Vpc terminal 17. The drains of transistors Q1 and Q2 are connected to bit lines 15.sub.1 and 15.sub.2, respectively. The gates of transistors Q1 and Q2 are both connected to ground. In a read mode, transistors Q1 and Q2 apply the potential Vpc of terminal 17 to bit lines 15.sub.1 and 15.sub.2, respectively.
Memory cell 18 includes N-channel MOS FETs Q3 and Q4 as drivers, N-channel MOS FETs Q5 and Q6 as transfer gates, and high-resistance load resistors R1 and R2. First terminals of transistors Q5 and Q6 are connected to bit lines 15.sub.1 and 15.sub.2, respectively. The gates of transistors Q5 and Q6 are both connected to word line 14. The sources of transistors Q3 and Q4 are both connected to ground. The gate of transistor Q3 is connected to the drain of transistor Q4, and the drain of transistor Q3 is connected to the gate of transistor Q4. The drains of transistors Q3 and Q4 are connected to the second terminals of transistors Q5 and Q6, respectively. High-resistance load resistor R1 is connected between the drain of transistor Q3 and power source V.sub.DD. High-resistance load resistor R2 is connected between the drain of transistor Q4 and power source V.sub.DD. Transistors Q3 and Q4 and high-resistance load resistor R1 and R2 make up a flip-flop. This flip-flop stores the data supplied from the pair of bit lines 15.sub.1 and 15.sub.2 via transistors Q5 and Q6.
Writing circuit 20 includes N-channel MOS FETs Q7 and Q8, both for line selection. The drains of transistors Q7 and Q8 are connected to bit lines 15.sub.1 and 15.sub.2, respectively. The sources of transistors Q7 and Q8 are connected to write control circuit 21 (FIG. 1) via write control lines 26.sub.1 and 26.sub.2, respectively. The gates of transistors Q7 and Q8 are supplied with the decode output of column decoder 23.
A decoding element for one row in row decoder 13, or a decoding element for one column (for a pair of bit lines 15.sub.1 and 15.sub.2) in column decoder 23 has the configuration shown in FIG. 3. Address signal Add is supplied to NAND gate 27. The logical state of the output of NAND gate 27 is inverted by inverter 28. The output of inverter 28, i.e., the output of decoder 13 or 23, is supplied to decode output line 29 (a word line or a column select line). When this output is at "1" level, the word line or the column select line is selected.
The operation of the SRAM shown in FIG. 1 will now be described. In a read mode, address signal Add is supplied to address input circuit 12 from address input termInal 11. The row address signal output from address input circuit 12 is supplied to row decoder 13. The column address signal output from address input cirCuit 12 is supplied to column decoder 23. On the basis of the decode output of row decoder 13, one word line 14 is selected. Memory cells 18, 18, . . . in the same row, that are connected to the selected word line 14, are then selected. Due to the stored data read out from the selected memory cells 18, 18, . . . , a potential difference occurs between paired bit lines 15.sub.1 and 15.sub.2. The potential difference is amplified by sense amplifier 19. Stored data D on the pair of bit lines 15.sub.1 and 15.sub.2 of the column selected by decoder 23 is output from data input/output terminal 25 via data input/output circuit 24. In the read-mode, write signal terminal 22 is at the read-mode level. Writing circuits 20, 20, . . . are made inoperable by the output of write control circuit 21.
A write operation progresses in the same way as that of the read operation until one word line 14 is selected. Write signal terminal 22 is at the write-mode level. The output of write control circuit 21 enables writing circuit 20 to be ready for the write operation. Data D supplied to data input/output terminal 25 is written via data input/output circuit 24 and column decoder 23 into memory cell 18 connected to the pair of bit lines 15.sub.1 and 15.sub.2 in the column which has been selected by column decoder 23.
FIG. 4 shows a prior art dynamic random access memory (abbreviated to DRAM). In the figure, the components similar to those in FIG. 1 are denoted by the same reference numerals. This memory differs from the SRAM in the connection of memory cells 30 to the peripheral circuits, and in the use of precharge circuit control signal line 31 between writing circuit 20 and precharge circuit 16. Precharge circuit 16, memory cell 30, and writing circuit 20 have configurations shown in FIG. 5. Precharge circuit 16 includes P-channel MOS FETs Q9 and Q10. The sources of transistors Q9 and Q10 are connected to precharge power source Vpc terminal 17. The drains of transistors Q9 and Q10 are connected to bit lines 15.sub.1 and 15.sub.2, respectively. The output of write control circuit 21 is supplied to the gates of transistors Q9 and Q10, via precharge control signal line 31.
Memory cell 30 includes N-channel MOS FET Q11 as a transfer gate, and capacitor C. The first terminal of transistor Q11 is connected to bit line 15.sub.1. The gate is connected to word line 14. Capacitor C is connected between the second terminal of transistor Q11 and ground. Data D supplied from bit line 15.sub.1 via transistor Q11 is stored in capacitor C. When the data D is at the "1" level, capacitor C is charged. When the data D is at the "0" level, capacitor C is not charged. Depending on the level of data D, the electric charge is present or absent in capacitor C.
Writing circuit 20 has the same configuration as that in the SRAM of FIG. 2. The decoding element for one row in row decoder 13, or the decoding element for one column (for a pair of bit lines 15.sub.1 and 15.sub.2) in Column deCoder 23 also has the configuration Shown in FIG. 3.
The write operation of the DRAM will be described. Prior to writing data, transistors Q9 and Q10 of precharge circuit 16 are turned on by the output signal of write control circuit 21, thereby precharging a pair of bit lines 15.sub.1 and 15.sub.2 to a level of VDD/2. The subsequent operation is the same as that of the SRAM.
In either prior art semiconductor memory device, it is possible to perform read and write operations for a memory cell as specified by one address. However, when the same data is to be written into all the memory cells (for example, memory cell data clear operation for writing data "0" into all the memory cells), it is necessary to sequentially perform the write operations for all memory cells, while changing the addresses. In the case of a 64K-bit semiconductor memory device, 2.sup.15 (=65536) address-inputting operations of 2.sup.15 (=65536) and the same number of data-writing operations are required. Since the semiconductor memory device cannot be used while the data is being cleared, a system using this semiconductor memory device (e.g., an image data processing system using a microcomputer) cannot operate efficiently.
As described above, the prior semiconductor memory device executes the address selection only once for one memory cell. Therefore, in a data clear mode, it needs much time for writing the same data into all memory cells.